In a common-source configuration, input is applied to the gate terminal and the output is taken from the drain terminal. Source terminal is common to both the input and the output sections.
Common-source configuration offers high input impedance, low output impedance, high voltage gain and the output voltage is 180° out-of-phase with the input voltage.
The commonly used common-source biasing configurations include fixed-bias configuration, self-bias configuration and voltage-divider configuration.
Fixed-bias configuration is the simplest of the biasing configurations. Figure below shows the fixed-bias circuit for n-channel JFET.
The biasing components include drain resistor (RD), gate resistor (RG), input and output coupling capacitors (Ci and Co), drain supply voltage (VDD) and gate supply voltage (VGG). The gate supply voltage ensures that the gate terminal is negative w.r.t. to the source. Resistor RG is used so that the input AC signal develops across it.
Fixed-bias circuit for n-channel JFET
Figure below shows the DC equivalent of a fixed-bias circuit.
DC equivalent of fixed-bias circuit
In a JFET, gate current (IG) is approximately equal to zero (IG ≅ 0 ). Therefore, the voltage drop across resistor RG is approximately zero.
Applying Kirchhoff’s voltage law to the input section we get
Therefore, the value of gate-source voltage is given by
The gate-source voltage (VGS) is negative and equal in magnitude to the applied gate voltage (VGG). As the voltage VGG is fixed, VGS is also fixed. Therefore, the configuration is named as fixed-bias configuration. This value of gate-source voltage is denoted as VGSQ.
Quiescent drain current (IDQ) is given by
Since the value of gate-source voltage (VGS) in this configuration is fixed, therefore the level of drain current (ID) is also fixed.
Applying Kirchhoff’s voltage law to the output section we get
Therefore, the value of quiescent drain-source voltage is given by
The operating point is defined as (IDQ, VDSQ). The value of operating point can be obtained by the following equations.
The operating point can be obtained graphically, by superimposing the vertical line VGS = –VGG on the transfer characteristics of the JFET as shown in Figure below.
Graphical analysis of the fixed-bias circuit
The operating point can also be obtained by superimposing the load line on the output characteristic curves of the JFET. The load line is defined by
Substituting VDS = 0 in above equation, we get ID = VDD/RD
Substituting ID = 0 in above equation, we get VDS = VDD
The line formed by joining the two points (0, VDD) and (VDD/RD, 0) is the DC load line. Figure below shows the load line analysis.
Load line analysis for the fixed-bias circuit
The fixed-bias configuration is not used much as the wide differences in the minimum and maximum values of the JFET parameters make drain current levels unpredictable for the fixed-bias circuit. Another disadvantage of the fixed-bias circuit is that it needs an additional supply voltage for biasing the gate terminal.
Self-bias configuration is the most commonly used biasing scheme for FETs as it offers stabilization of the operating point against variations in FET parameters.
Self-bias configuration circuit is similar to fixed-bias circuit except for the addition of source resistor (RS) between the source and the ground terminals and the removal of the gate supply voltage. Figure below shows the circuit. The voltage drop across the resistor (RS) provides the controlling gate voltage.
Self-bias configuration for n-channel JFET
DC equivalent of the self-bias circuit is shown in Figure below.
DC equivalent of self-bias configuration
As IG = 0, there is no voltage drop across the resistor RG. Therefore, gate voltage VG = 0. Applying Kirchhoff’s voltage law to the input section we get
Therefore,
As the gate voltage is zero, the source voltage (VS) is given by
The voltage drop (VS) across source resistor RS provides the biasing gate-source voltage and hence no external power supply is required for the purpose. Hence this configuration is named self-bias configuration. The voltage (VS) also results in bias-point stabilization. If the transconductance of the JFET decreases, the drain current decreases resulting in decrease in the voltage across resistor RS. Thus, the voltage VGS becomes less negative resulting in increase in drain current. This compensates for the initial decrease in the drain current.
Drain current (ID) is given by
or
Applying Kirchhoff’s voltage law to the output section we get
Therefore, the drain-source voltage (VDS) is given by
Operating point can be obtained from the following equations.
Graphical analysis can also be done for obtaining operating point. The graphical analysis (refer to figure below) is done in a similar manner to that for fixed-bias configuration. The operating point is determined by superimposing the straight line corresponding to the equation VGS = -IDRS on the transfer characteristic curve of the JFET.
Graphical analysis of self-bias configuration for n-channel JFETs
Load line analysis for self-bias circuit can also be done in the same manner as done for the fixed-bias circuit. The only difference is that the load line is now defined by
The voltage-divider biasing configuration for n-channel JFET is shown in figure below.
The resistors R1 and R2 form the potential divider and voltage across resistor R2 provides necessary bias to the JFET.
Voltage-divider biasing configuration for n-channel JFETs
Figure below shows the DC equivalent circuit for the voltage-divider biasing configuration for an n-channel JFET.
DC equivalent of voltage-divider biasing configuration
As the gate current IG ≅ 0, the gate voltage is given by
The gate-source voltage (VGS) is given by
As the gate-source voltage should be negative for proper operation of n-channel JFETs, therefore for the circuit to operate properly the voltage (ID X RS) should be larger than voltage VG.
Applying Kirchhoff’s voltage law to the output section we get
The operating point is given by
Figure below shows the graphical method to determine the operating point. Load line analysis can also be done to establish the operating point as explained in the case of fixed-bias circuit.
Graphical analysis of voltage-divider bias configuration